Microarchitecture & security
Discovering how hidden processor behavior exposes information, and developing hardware defenses that learn from execution.
Computer architecture · Hardware security · AI
Assistant Professor, Electrical & Computer Engineering
Faculty Member, Computer Science
North Carolina State University
smirbag@ncsu.edu
I study how processors learn, perform, and leak information—and how to build computer systems that are faster, more efficient, and more secure.

I am an Assistant Professor in Electrical and Computer Engineering at North Carolina State University, where I lead the BRAIN SPEC research lab. I am also a faculty member in Computer Science and am affiliated with NC State’s Secure Computing Institute.
My work brings together computer architecture, systems security, and machine learning. I investigate the mechanisms behind processor behavior and use those insights to design efficient hardware, uncover security weaknesses, and develop defenses.
I especially enjoy advising graduate and undergraduate students in research and helping them grow as independent researchers.
University of California Postdoctoral Fellow
UC San Diego, Computer Science & Engineering
Ph.D., Computer Science
Texas A&M University
B.S., Computer Engineering
University of Isfahan
Discovering how hidden processor behavior exposes information, and developing hardware defenses that learn from execution.
Investigating the security consequences of performance optimizations in on-chip accelerators, including data-dependent timing, sparsity, and power gating.
Developing compact learning mechanisms and tools that help architects explain hardware behavior and improve processor performance.

Professional service news · Graduate committee news · Professional memberships

Interactive reasoning over cache traces, with a benchmark for evaluating explanations of microarchitectural behavior.
How sparsity optimizations can expose private features through the timing of AI inference.
Top Picks from the 2025 computer architecture conferencesIEEE Micro Top Picks article, with the original MICRO paper and impact summary in one PDF bundle.
Selected for IEEE Micro Top PicksA study of the security and privacy consequences of power gating in Intel AMX, and the tradeoffs involved in mitigation.
Three artifact-evaluation badges · MICRO 2025
GateBleed earned Artifacts Available; Artifacts Evaluated — Functional; Results Reproduced.



Characterizing how operand values influence matrix-accelerator timing and create information leakage.
Adaptive hardware detection strengthened through the generation and study of evasive attacks.
Using microarchitectural observations and compact hardware learning to detect attacks before information is leaked.
My courses connect processor design, security, and machine learning through measurement and hands-on investigation. Students build experiments, question assumptions, and develop research ideas from the behavior of real systems.
Teaching resourcesECE 492/592 · Fall 2026
Experimental methods for understanding processors, investigating side channels, and evaluating hardware security.
Undergraduate & graduate teaching
Connecting generative AI with systems questions, experimental evaluation, and computer architecture research.
BRAIN SPEC Lab
I mentor graduate and undergraduate researchers in hardware security and computer architecture. Our work brings together careful measurement, causal explanations, and reproducible artifacts.
Meet the research groupFor research collaborations, academic inquiries,
and prospective student interests.
Electrical & Computer Engineering · Computer Science
North Carolina State University
Office phone: 919-515-4088
Campus mail: Box 7911